Static random access memory (SRAM) cells can be implemented using cross-coupled logic gates which maintain logic states representing data values. Ideally, SRAM cells should hold their stored logic states despite possible changes in voltage, temperature, or other operating conditions. Unfortunately, existing SRAM cell designs often fail to provide high degrees of read stability.
As SRAM cell operating voltages are reduced, the internal nodes of the SRAM cell may be vulnerable to read disturbance. For example, during a read operation, the internal SRAM nodes may be inadvertently charged through the access transistors to rise above a trip voltage of the SRAM cell, thereby causing the SRAM cell to inadvertently switch logic states.
The Static Noise Margin (SNM) is a “figure of merit” which measures read stability and read margin. See Benton H. Calhoun and Anantha Chandrakasan, Analyzing Static Noise Margin for Sub-threshold SRAM in 65 nm CMOS, http://www-mtl.mit.edu/researchgroups/icsystems/pubs/conferences/2005/bcalhoun_esscirc2005_paper.pdf (September 2005). See also Evert Seevinck, Frans J. List, Jan Lohstroh, Static-Noise Margin Analysis of MOS SRAM Cells, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-22, No. 5, pp. 748-754 (October 1987).
Essentially, designers aim for the most symmetrical SNM curve that is possible, with the widest “eye.” The “eye” is the gap between the lowest logic high and the highest logic low voltages that form the SNM curve. A symmetrical SNM curve with a wide “eye” represents strong read stability, optimal read margin, and minimal read disturbance. Conversely, an asymmetrical graph with a reduced eye represents low read stability, minimal read margin, and high read disturbance. Therefore, to improve read margin, a designer's goal is to achieve a symmetrical SNM curve with the widest eye possible.
To minimize read disturbance, increase read stability, improve read margin, and improve the SNM, a designer can reduce the ratio between the sizes of the NMOS driver transistor and the NMOS pass transistor in a SRAM cell. However, when NMOS transistors are manufactured in a modern manufacturing process (e.g. a 65 nm process), the variation from the desired ratio between the driver and the pass transistor can be significant. For example, in NMOS transistors manufactured in a 65 nm process, the variation from the desired ratio can be as large as 10:1. These large variations lead to differences in resistance, channel length, threshold voltage, and other device characteristics. Large variations in size ratios and device characteristics are a major cause of low read stability.
In one approach to reduce read disturbance, improve read stability, and increase read margin, an additional pair of PMOS transistors is added to the SRAM cell so that the overall ratio of the PMOS transistors to the NMOS transistors in the SRAM cell is minimized. The additional pair of PMOS transistors also makes the SNM curve symmetrical, resulting in a wider “eye.” This approach tries to minimize the variation in size ratio between the NMOS driver and pass transistors by counter-balancing voltages in the SRAM cell. Although adding a pair of PMOS transistors alleviates the problem slightly, such an approach has its own drawbacks. The PMOS transistors eventually get so strong that they pull nodes in the SRAM cell high when they should not be pulled high, leading to poor read stability.
In another approach to reduce read disturbance and improve read stability, the variations in device characteristics are reduced by a “Dual Stress Layer” in selected transistors (e.g. a pass gate transistor) of a SRAM cell. See Shou-Gwo Wuu, Jin-Yuan Lee, Dun-Nian Yaung, Jeng-Han Lee, U.S. Pat. No. 6,635,936 (“SRAM Layout for Relaxing Mechanical Stress in Shallow Trench Isolation Technology”); Mark Craig, Karsten Wieczorek, Manfred Horstmann, WO/2007/018780 (“SRAM Devices Utilizing Tensile-Stressed Strain Films”). However, this approach restricts the variations in device characteristics only from a device physics perspective. This approach does not address the larger problem of voltage and size ratio variance in a SRAM cell that leads to read instability, higher read disturbance, and a lower SNM.
As can be seen, both adding a pair of PMOS transistors and a solution aimed at altering the device characteristics of SRAM transistors are problematic.